ZurichHW #1

Arianna Rubino and Frank Kagan Gürkaynak (ETH Zurich): Integrated circuit design for everyone: end-to-end open-source hardware design

The electronics design industry and the prevalence of integrated circuits (ICs) has transformed our daily lives significantly. However, the design of ICs still remains inaccessible to even most higher education institutions and small and medium-sized enterprises (SMEs) due to the need of proprietary electronic design automation (EDA) tools, NDA-restricted process design kits (PDKs) and closed intellectual property.

End-to-end open-source hardware design changes this: every step, from the foundry’s PDK to the tools that turn a circuit idea into a manufacturable layout, is openly available to anyone. This lowers the barrier for students and small companies and makes designs easy to share between universities and companies.

In this talk, Frank and Arianna present the work of the Microelectronics Design Center (ETH Zurich) and Prof. Luca Benini’s PULP team (ETH Zurich and University of Bologna) on the development of a fully open design flow for both digital and analog/mixed-signal circuits. The flow is built on IHP’s open 130 nm technology, with open tools such as Yosys and OpenROAD for digital design and Xschem and KLayout for analog design.

They will first discuss what open flows and openly shareable designs mean for the community, then talk about few chips designed and fabricated end to end with open tools:

• Croc, a customizable RISC-V microcontroller platform with which more than 65 students each year produce around 30 manufacturable designs in a single course, a selection of which are fabricated;
• Basilisk, a 34 mm², Linux-capable 64-bit RISC-V SoC and the largest end-to-end open-source chip reported to date;
• Ristretto, their first open-source mixed-signal chip, combining an analog front-end with spiking neurons for event-based sensing and marking the start of a series of open-source mixed-signal designs.

Filippo Moro (UZH / ETH Zurich): Co-designing chips and neural networks for autonomous robots

Small autonomous robots operate under tight energy and latency constraints that traditional AI and computing systems struggle to meet. A duck-sized robot spends watts on computation, while a real duck runs its brain on a fraction of a watt, more than an order of magnitude less. Much of this gap comes from off-the-shelf processors that constantly shuttle data to and from external DRAM, where a single memory access can cost orders of magnitude more energy than the computation it serves.

In this talk, I will present my vision for closing this gap by co-designing neural networks and the silicon that runs them. The guiding principle is to split the robot’s computation by function and build dedicated circuits for each part.

Sensory perception, such as vision and audition, is largely stable over time, and I propose to bake it directly into logic gates, supported by self-supervised encoders that are robust to sensory noise. Behavior, in contrast, must be flexible: a multi-core in-memory computing architecture offers a natural substrate for hosting many locomotion and behavioral policies on-chip, instantly switchable and composable.

Ultimately, I envision heterogeneous chips that give small robots the perception and agility they need within a biologically plausible energy budget.