HDL Developer
Xiper · Zurich, Switzerland / Munich, Germany
About
Develop reusable FPGA components for XiperLib, covering arithmetic, filtering, transforms and communications.
Responsibilities
- Design, implement and verify reusable RTL components.
- Improve component quality, performance and verification.
- Shape the design of the XiperLib FPGA component library.
Requirements
- Strong Verilog or VHDL skills.
- Solid verification skills.
- A focus on clean, correct FPGA designs.