MSc Thesis / Semester Project
Xiper · Zurich, Switzerland / Munich, Germany
About
Explore AI, FPGA design or compiler development through an MSc thesis or semester project for ETH Zurich students.
Project topics
- Use AI to port OpenCV kernels to FPGA and assess bit-exact results.
- Compare open-weight and frontier models on hardware specifications.
- Develop checks that AI cannot game.
- Develop compiler passes for XiperPy.
Requirements
- Study electrical engineering, computer science or a related subject at ETH Zurich.
- An interest in FPGA design, compilers or AI.
- Specify a preferred topic when applying, or propose your own.