ETH Zurich researchers published benchmarks for EZ130 8T, an open library of 220 reusable circuit cells for IHP's 130nm chip-manufacturing process. In a post-layout matrix-multiplier comparison, the design used 35% less cell area and an estimated 39% less energy than the reference library, with a roughly 3% longer clock period.
Developed by students in a 2025 VLSI course, the library is available under Apache 2.0 and lets designers build chips from transistor-level components through automated design tools. Two chips using earlier versions passed initial tests, but full characterization is still underway. The reported efficiency gains come from design analysis, not measured silicon performance; the September preprint documents the results rather than marking the library's creation.
